(1) Field of the Invention
This invention relates to a random access memory device and, more particularly, to a method of forming an array of closely spaced stacked capacitors having increased capacitance.
(2) Description of the Prior Art
Very large scale integration (VLSI) semiconductor technologies have dramatically increased the circuit density on the chip. The miniaturized devices built in and on the semiconductor substrate, making up these circuits, are very closely spaced and their packing density has increased significantly. Future requirements for even greater increases in packing density is putting additional demand on the semiconductor technologies and more particularly on the photolithographic techniques.
One such circuit element experiencing increasing demand for higher packing density is the array of storage cells on a dynamic random access memory (DRAMs) chip. These individual DRAM storage cells, consisting usually of a single metal-oxide-semiconductor field-effect transistor (MOSFET) and a single capacitor, are used extensively in the electronics industry for storing data. A single DRAM storage cell stores a bit of data on the capacitor as electrical charge.
However, as the array of cells on the DRAM chip increase in number and the capacitor decrease in size, it becomes increasingly difficult to maintain sufficient charge on the storage capacitor to maintain an acceptable signal-to-noise level. Also, these volatile storage cells require more frequent refresh cycles to retain their charge.
These storage capacitors can be formed either in the substrate, usually referred to as trench capacitors, or by forming stacked capacitors on the substrate after first fabricating the field effect transistors. The latter method has received considerable attention in recent years. However, since each capacitor in the array of storage cells are confined within the cell area, it is difficult to maintain sufficient capacitance as the cell size decreases. Therefore, it becomes necessary to explore other methods for increasing the capacitance.
Some methods for increasing capacitance include, building a three dimensional capacitor structure extending vertically upward over the cell area. For example, see H-H Tseng U.S. Pat. No. 5,192,702 and C. H. Dennison et al U.S. Pat. No. 5,061,650. Another approach is to roughen the surface of the bottom electrode of the capacitor to effectively increase the surface area without increasing its overall size. For example, see H. C. Tuan et al U.S. Pat. No. 5,266,514. Still another approach is to use interelectrode insulators having high dielectric constants. For example see the publication "A Newly Designed Planar Stacked Capacitor Cell with High Dielectric Constant Film for 256 Mbit DRAM" by T. Eimori et al IEEE International Electron Device Meeting Proceedings, December 1993 pages 631-634.
However, it is still desirable to retain as simple a process as possible to maintain high chip yields, low cost and good reliability. Also, it would be very desirable to extend the resolution of current photolithographic limits to reduce the spacing between adjacent cell capacitors while increasing the capacitor area and at the same time taking advantage of the other technologies, such as roughened surface area and using inter-electrode high dielectric insulators.